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dc.contributor.authorRathnala, Prasanthi
dc.contributor.authorWilmshurst, Tim
dc.contributor.authorKharaz, Ahmad H.
dc.date.accessioned2018-12-06T14:55:31Z
dc.date.available2018-12-06T14:55:31Z
dc.date.issued2018-12-06
dc.identifier.citationRathnala, P., Wilmshurst, T., and Kharaz, A. (2018) 'Timing error detection and correction for power efficiency: an aggressive scaling approach', IET Circuits, Devices & Systems, 12(6), p.p. 707-712, doi: 10.1049/iet-cds.2018.5143en
dc.identifier.issn1751-858X
dc.identifier.doi10.1049/iet-cds.2018.5143
dc.identifier.urihttp://hdl.handle.net/10545/623195
dc.description.abstractLow-power consumption has become an important aspect of processors and systems design. Many techniques ranging from architectural to system level are available. Voltage scaling or frequency boosting methods are the most effective to achieve low-power consumption as the dynamic power is proportional to the frequency and to the square of the supply voltage. The basic principle of operation of aggressive voltage scaling is to adjust the supply voltage to the lowest level possible to achieve minimum power consumption while maintaining reliable operations. Similarly, aggressive frequency boosting is to alter the operating frequency to achieve optimum performance improvement. In this study, an aggressive technique which employs voltage or frequency varying hardware circuit with the time-borrowing feature is presented. The proposed technique double samples the data to detect any timing violations as the frequency/voltage is scaled. The detected violations are masked by phase delaying the flip-flop clock to capture the late arrival data. This makes the system timing error tolerant without incurring error correction timing penalty. The proposed technique is implemented in a field programmable gate array using a two-stage arithmetic pipeline. Results on various benchmarks clearly demonstrate the achieved power savings and performance improvement.
dc.description.sponsorshipN/Aen
dc.language.isoenen
dc.publisherIETen
dc.relation.urlhttps://doi.org/10.1049/iet-cds.2018.5143
dc.rightsArchived with thanks to IET Circuits, Devices & Systemsen
dc.rights"This paper is a postprint of a paper submitted to and accepted for publication in IET Circuits, Devices and Systems and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at the IET Digital Library"
dc.subjectError detectionen
dc.subjectError correctionen
dc.subjectLow-power electronicsen
dc.subjectField programmable gate arraysen
dc.titleTiming error detection and correction for power efficiency: an aggressive scaling approachen
dc.typeArticleen
dc.identifier.eissn1751-8598
dc.contributor.departmentUniversity of Derbyen
dc.identifier.journalIET Circuits, Devices & Systemsen
dcterms.dateAccepted2018-09-06
refterms.dateFOA2019-02-28T17:53:56Z
html.description.abstractLow-power consumption has become an important aspect of processors and systems design. Many techniques ranging from architectural to system level are available. Voltage scaling or frequency boosting methods are the most effective to achieve low-power consumption as the dynamic power is proportional to the frequency and to the square of the supply voltage. The basic principle of operation of aggressive voltage scaling is to adjust the supply voltage to the lowest level possible to achieve minimum power consumption while maintaining reliable operations. Similarly, aggressive frequency boosting is to alter the operating frequency to achieve optimum performance improvement. In this study, an aggressive technique which employs voltage or frequency varying hardware circuit with the time-borrowing feature is presented. The proposed technique double samples the data to detect any timing violations as the frequency/voltage is scaled. The detected violations are masked by phase delaying the flip-flop clock to capture the late arrival data. This makes the system timing error tolerant without incurring error correction timing penalty. The proposed technique is implemented in a field programmable gate array using a two-stage arithmetic pipeline. Results on various benchmarks clearly demonstrate the achieved power savings and performance improvement.


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