• Field programmable gate arrays-based number plate binarization and adjustment for automatic number plate recognition systems

      Zhai, Xiaojun; Bensaali, Faycal; Sotudeh, Reza; University of Hertfordshire (2013-01-15)
    • Improved number plate character segmentation algorithm and its efficient FPGA implementation

      Zhai, Xiaojun; Bensaali, Faycal; University of Hertfordshire (Springer, 2012-06-10)
      Character segmentation is an important stage in Automatic Number Plate Recognition systems as good character separation leads to a high recognition rate. This paper presents an improved character segmentation algorithm based on pixel projection and morphological operations. An efficient architecture based on the proposed algorithm is also presented. The architecture has been successfully implemented and verified using the Mentor Graphics RC240 FPGA (Field Programmable Gate Arrays) development board equipped with a 4M-Gate Xilinx Virtex-4 LX40. A database of 1,000 UK binary NPs with varying resolution has been used for testing the performance of the proposed architecture. Results achieved have shown that the proposed architecture can process a number plate image in 0.2–1.4 ms with 97.7 % successful segmentation rate and consumes only 11 % of the available area in the used FPGA.
    • Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation

      Zhai, Xiaojun; Ramalingam, Soodamani; Bensaali, Faycal; University of Hertfordshire (The Institution of Engineering and Technology, 2013-03-01)
      Number plate localisation is a very important stage in an automatic number plate recognition (ANPR) system and is computationally intensive. This study presents a low complexity with high-detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplier-less architecture based on that algorithm. The proposed architecture has been successfully implemented and tested using a Mentor Graphics RC240 FPGA (field programmable gate arrays) development board equipped with a 4M-gate Xilinx Virtex-4 LX40. Two database sets sourced from the UK and Greece and including 1000 and 307 images, respectively, both with a resolution of 640 x 480, have been used for testing. Results achieved have shown that the proposed system can process an image in 4.7 ms, while achieving a 97.8% detection rate and consuming only 33% of the available area of the FPGA.
    • Real-time optical character recognition on field programmable gate array for automatic number plate recognition system

      Sotudeh, Reza; Zhai, Xiaojun; Bensaali, Faycal; University of Hertfordshire (The Institution of Engineering and Technology, 2013-11-01)
      The last main stage in an automatic number plate recognition system (ANPRs) is optical character recognition (OCR), where the number plate characters on the number plate image are converted into encoded texts. In this study, an artificial neural network-based OCR algorithm for ANPR application and its efficient architecture are presented. The proposed architecture has been successfully implemented and tested using the Mentor Graphics RC240 field programmable gate arrays (FPGA) development board equipped with a 4M Gates Xilinx Virtex-4 LX40. A database of 3570 UK binary character images have been used for testing the performance of the proposed architecture. Results achieved have shown that the proposed architecture can meet the real-time requirement of an ANPR system and can process a character image in 0.7 ms with 97.3% successful character recognition rate and consumes only 23% of the available area in the used FPGA.