Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation

Hdl Handle:
http://hdl.handle.net/10545/583879
Title:
Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation
Authors:
Zhai, Xiaojun ( 0000-0002-1030-8311 ) ; Ramalingam, Soodamani; Bensaali, Faycal ( 0000-0002-9273-4735 )
Abstract:
Number plate localisation is a very important stage in an automatic number plate recognition (ANPR) system and is computationally intensive. This study presents a low complexity with high-detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplier-less architecture based on that algorithm. The proposed architecture has been successfully implemented and tested using a Mentor Graphics RC240 FPGA (field programmable gate arrays) development board equipped with a 4M-gate Xilinx Virtex-4 LX40. Two database sets sourced from the UK and Greece and including 1000 and 307 images, respectively, both with a resolution of 640 x 480, have been used for testing. Results achieved have shown that the proposed system can process an image in 4.7 ms, while achieving a 97.8% detection rate and consuming only 33% of the available area of the FPGA.
Affiliation:
University of Hertfordshire
Citation:
Zhai, X, Bensaali, F, & Ramalingam, S n.d., 'Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation', Iet Circuits Devices & Systems, 7, 2, pp. 93-103
Publisher:
The Institution of Engineering and Technology
Journal:
IET Circuits, Devices & Systems
Issue Date:
1-Mar-2013
URI:
http://hdl.handle.net/10545/583879
DOI:
10.1049/iet-cds.2012.0064
Additional Links:
http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2012.0064
Type:
Article
Language:
en
Series/Report no.:
Vol. 7; Issue 2
ISSN:
1751-858X; 1751-8598
Appears in Collections:
Department of Mechanical Engineering & the Built Environment

Full metadata record

DC FieldValue Language
dc.contributor.authorZhai, Xiaojunen
dc.contributor.authorRamalingam, Soodamanien
dc.contributor.authorBensaali, Faycalen
dc.date.accessioned2015-12-14T10:53:56Z-
dc.date.available2015-12-14T10:53:56Zen
dc.date.issued2013-03-01-
dc.identifier.citationZhai, X, Bensaali, F, & Ramalingam, S n.d., 'Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation', Iet Circuits Devices & Systems, 7, 2, pp. 93-103en
dc.identifier.issn1751-858X-
dc.identifier.issn1751-8598-
dc.identifier.doi10.1049/iet-cds.2012.0064-
dc.identifier.urihttp://hdl.handle.net/10545/583879-
dc.description.abstractNumber plate localisation is a very important stage in an automatic number plate recognition (ANPR) system and is computationally intensive. This study presents a low complexity with high-detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplier-less architecture based on that algorithm. The proposed architecture has been successfully implemented and tested using a Mentor Graphics RC240 FPGA (field programmable gate arrays) development board equipped with a 4M-gate Xilinx Virtex-4 LX40. Two database sets sourced from the UK and Greece and including 1000 and 307 images, respectively, both with a resolution of 640 x 480, have been used for testing. Results achieved have shown that the proposed system can process an image in 4.7 ms, while achieving a 97.8% detection rate and consuming only 33% of the available area of the FPGA.en
dc.language.isoenen
dc.publisherThe Institution of Engineering and Technologyen
dc.relation.ispartofseriesVol. 7en
dc.relation.ispartofseriesIssue 2en
dc.relation.urlhttp://digital-library.theiet.org/content/journals/10.1049/iet-cds.2012.0064en
dc.rightsArchived with thanks to IET Circuits, Devices & Systemsen
dc.subjectImage processingen
dc.subjectFPGAen
dc.subjectRecognitionen
dc.titleImproved number plate localisation algorithm and its efficient field programmable gate arrays implementationen
dc.typeArticleen
dc.contributor.departmentUniversity of Hertfordshireen
dc.identifier.journalIET Circuits, Devices & Systemsen
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