Improved number plate character segmentation algorithm and its efficient FPGA implementation

Hdl Handle:
http://hdl.handle.net/10545/583878
Title:
Improved number plate character segmentation algorithm and its efficient FPGA implementation
Authors:
Zhai, Xiaojun ( 0000-0002-1030-8311 ) ; Bensaali, Faycal ( 0000-0002-9273-4735 )
Abstract:
Character segmentation is an important stage in Automatic Number Plate Recognition systems as good character separation leads to a high recognition rate. This paper presents an improved character segmentation algorithm based on pixel projection and morphological operations. An efficient architecture based on the proposed algorithm is also presented. The architecture has been successfully implemented and verified using the Mentor Graphics RC240 FPGA (Field Programmable Gate Arrays) development board equipped with a 4M-Gate Xilinx Virtex-4 LX40. A database of 1,000 UK binary NPs with varying resolution has been used for testing the performance of the proposed architecture. Results achieved have shown that the proposed architecture can process a number plate image in 0.2–1.4 ms with 97.7 % successful segmentation rate and consumes only 11 % of the available area in the used FPGA.
Affiliation:
University of Hertfordshire
Citation:
Zhai, X, & Bensaali, F 2015, 'Improved number plate character segmentation algorithm and its efficient FPGA implementation', Journal Of Real-Time Image Processing, 1, p. 91
Publisher:
Springer
Journal:
Journal of Real-Time Image Processing
Issue Date:
10-Jun-2012
URI:
http://hdl.handle.net/10545/583878
DOI:
10.1007/s11554-012-0258-5
Additional Links:
http://link.springer.com/10.1007/s11554-012-0258-5
Type:
Article
Language:
en
Series/Report no.:
Vol. 10; Issue 1
ISSN:
1861-8200; 1861-8219
Appears in Collections:
Department of Mechanical Engineering & the Built Environment

Full metadata record

DC FieldValue Language
dc.contributor.authorZhai, Xiaojunen
dc.contributor.authorBensaali, Faycalen
dc.date.accessioned2015-12-14T10:49:25Z-
dc.date.available2015-12-14T10:49:25Zen
dc.date.issued2012-06-10-
dc.identifier.citationZhai, X, & Bensaali, F 2015, 'Improved number plate character segmentation algorithm and its efficient FPGA implementation', Journal Of Real-Time Image Processing, 1, p. 91en
dc.identifier.issn1861-8200-
dc.identifier.issn1861-8219-
dc.identifier.doi10.1007/s11554-012-0258-5-
dc.identifier.urihttp://hdl.handle.net/10545/583878-
dc.description.abstractCharacter segmentation is an important stage in Automatic Number Plate Recognition systems as good character separation leads to a high recognition rate. This paper presents an improved character segmentation algorithm based on pixel projection and morphological operations. An efficient architecture based on the proposed algorithm is also presented. The architecture has been successfully implemented and verified using the Mentor Graphics RC240 FPGA (Field Programmable Gate Arrays) development board equipped with a 4M-Gate Xilinx Virtex-4 LX40. A database of 1,000 UK binary NPs with varying resolution has been used for testing the performance of the proposed architecture. Results achieved have shown that the proposed architecture can process a number plate image in 0.2–1.4 ms with 97.7 % successful segmentation rate and consumes only 11 % of the available area in the used FPGA.en
dc.language.isoenen
dc.publisherSpringeren
dc.relation.ispartofseriesVol. 10en
dc.relation.ispartofseriesIssue 1en
dc.relation.urlhttp://link.springer.com/10.1007/s11554-012-0258-5en
dc.rightsArchived with thanks to Journal of Real-Time Image Processingen
dc.subjectImage processingen
dc.subjectFPGAen
dc.subjectAutomatic number plate recognitionen
dc.subjectCharacter segmentationen
dc.titleImproved number plate character segmentation algorithm and its efficient FPGA implementationen
dc.typeArticleen
dc.contributor.departmentUniversity of Hertfordshireen
dc.identifier.journalJournal of Real-Time Image Processingen
All Items in UDORA are protected by copyright, with all rights reserved, unless otherwise indicated.